Speeding Up RISC-V with Open-Source Storage

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Author: Denis Avetisyan

A new open-source SD host controller implementation for RISC-V SoCs delivers significant performance gains and reduced silicon footprint.

This paper details the implementation and optimization of an SDHC/SDHCI controller for the Cheshire RISC-V SoC, demonstrating improved persistent storage access compared to SPI.

While fully open-source RISC-V systems-on-chip are increasingly viable, efficient non-volatile storage remains a critical challenge beyond basic SPI interfaces. This paper, ‘Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs’, details the design and optimization of an open-source SD host controller (SDHCI) integrated into the Cheshire RISC-V SoC platform, achieving up to 11.1 MB/s throughput-a six-fold improvement over SPI-based storage. Through careful analysis of the CVA6 memory system and customized driver implementation, we mitigated performance bottlenecks caused by inefficient fence instruction handling during memory-mapped register accesses. Can this approach unlock further performance gains and broader applicability for persistent storage in open-source RISC-V ecosystems?

Foundations for Adaptable Systems

The increasing ubiquity of embedded systems – from smart appliances and automotive components to industrial controllers and medical devices – necessitates hardware platforms capable of adaptation and rigorous scrutiny. Unlike general-purpose computing, where software often abstracts hardware complexities, embedded systems demand precise control and optimization at the physical layer. This creates a critical need for designs that are not merely functional, but also readily customizable to specific application requirements and, crucially, verifiable for both security and reliability. The sheer scale of deployment means even minor vulnerabilities or inefficiencies can have widespread consequences, making flexible and auditable hardware a foundational element for continued innovation and trustworthy operation across a multitude of sectors.

Historically, hardware development has relied heavily on proprietary designs, a practice that inherently restricts user agency and stifles progress. These closed systems often present limited opportunities for modification, forcing users to accept pre-defined functionalities and hindering attempts at optimization for specific applications. More significantly, reliance on a single vendor for crucial components creates a form of ‘lock-in’, where switching to alternative solutions becomes economically or technically prohibitive. This dependence not only limits innovation but also introduces vulnerabilities, as users are reliant on the vendor for bug fixes, security updates, and long-term support. The constraints of proprietary hardware, therefore, represent a significant barrier to both independent research and the rapid prototyping necessary for cutting-edge technological advancements.

The burgeoning field of open-source hardware is significantly reshaping the landscape of technological development, and the RISC-V instruction set architecture provides a compelling example of this shift. Unlike traditionally closed, proprietary hardware designs, RISC-V offers a freely available and extensible foundation for creating custom processors and systems. This openness encourages a collaborative environment where engineers, researchers, and hobbyists worldwide can contribute to the architecture’s refinement and build specialized hardware solutions without restrictive licensing fees or vendor dependencies. The result is a dramatically accelerated pace of innovation, as modifications and improvements are rapidly shared and integrated, fostering a diverse ecosystem of tailored hardware for everything from embedded devices and machine learning accelerators to high-performance computing – a stark contrast to the slower, more controlled development cycles characteristic of closed-source alternatives.

Cheshire: A Platform for SDHC Analysis

The Cheshire System-on-Chip (SoC) provides a flexible hardware environment for SD Host Controller (SDHC) integration and performance analysis. Its architecture allows for the instantiation and testing of various SDHC configurations, supporting different SD card interfaces and operating modes. The platform’s modular design facilitates the evaluation of SDHC implementations against industry standards and allows for the assessment of performance metrics such as data transfer rates and latency. Furthermore, the SoC enables the testing of SDHC functionality under diverse operating conditions, including varying voltage levels and temperature ranges, providing a comprehensive validation environment before deployment in end products.

The Secure Digital Host Controller Interface (SDHCI) standard is fundamental to the interoperability of SDHC integration within the Cheshire platform. This standard rigorously defines a 32-bit register map, specifying memory-mapped registers used for controller configuration, data transfer control, and status reporting. Precise timing parameters for interrupt generation are also mandated by the SDHCI standard, governing how the host controller signals events such as card detection, data request completion, and error conditions. Adherence to these specifications ensures compatibility with a wide range of SD and SDIO cards, and is a prerequisite for successful data communication and system operation.

The implementation of the SDHC within the Cheshire platform benefits from the use of open-source Electronic Design Automation (EDA) tools, specifically Yosys for synthesis and OpenROAD for place and route. Yosys, a framework for RTL synthesis, allows for the conversion of hardware description code into a netlist, while OpenROAD automates the physical design aspects of chip implementation. This toolchain eliminates the costs associated with proprietary software licenses and enables full visibility and control over the design process. Furthermore, the scriptability of both Yosys and OpenROAD facilitates automated design exploration, regression testing, and the integration of custom verification flows, accelerating the development cycle and improving design quality.

Rapid prototyping and iterative design cycles are enabled by the Cheshire platform’s integration of the SDHC, allowing for focused investigation of performance optimizations. This methodology facilitates quick implementation of design modifications – such as adjustments to data transfer modes, clock frequencies, or register configurations – followed by immediate hardware-level testing. The speed of this process reduces the turnaround time for evaluating different architectural choices and their impact on SD card read/write speeds, latency, and overall system throughput. Consequently, developers can efficiently explore a wider range of optimization strategies than would be possible with traditional, slower design workflows.

Performance Characterization and Optimization

Bare-metal execution, employed for initial performance characterization, involves running the system’s firmware directly on the hardware without the intervention of a host operating system or hypervisor. This methodology eliminates operating system-level overhead – including task scheduling, memory management, and system calls – providing a baseline measurement of raw hardware performance. By isolating the firmware and directly accessing hardware resources, this approach yields deterministic and reproducible results, crucial for identifying inherent performance limitations and optimizing critical code paths before introducing the complexities of a full software stack. The resulting metrics accurately reflect the capabilities of the hardware and firmware combination in an unconstrained environment.

Following bare-metal performance characterization, testing was conducted within a Linux operating system environment configured with the Ext4 file system to assess performance under more typical operating conditions. This testing yielded a measured read throughput of 945 kB/s and a write throughput of 485 kB/s. These values represent the sustained data transfer rates achieved during read and write operations to the Ext4 partition within the Linux environment, providing a benchmark for real-world application performance.

The AXI Crossbar serves as a central component for performance optimization by facilitating a high-bandwidth interface to the memory system. This interconnect allows multiple master devices to simultaneously access memory without contention, increasing overall system throughput. Specifically, the AXI Crossbar enables parallel data transfers, bypassing potential bottlenecks associated with single-path memory access. Its configuration supports multiple AXI slaves, enabling efficient data flow between processing elements and memory, and is configurable to prioritize certain transactions based on application requirements.

The implementation of SD DMA and HPDcache is designed to optimize data handling within the system by leveraging the CMO (Common Memory Observer). SD DMA facilitates efficient data transfers by allowing direct memory access without CPU intervention, thereby reducing latency and freeing processor cycles. HPDcache, integrated with SD DMA, provides a high-performance data cache managed through CMO, which intelligently stores frequently accessed data closer to the processing unit. This combination reduces average memory access times and increases overall throughput by minimizing the need to access slower external memory, ultimately enhancing system performance through optimized data flow and reduced latency.

Benchmarking and the Value of Efficiency

To accurately assess its capabilities, the Serial Digital Host Controller (SDHC) underwent rigorous benchmarking against established serial communication protocols – Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C) – all implemented on the identical Cheshire System-on-Chip (SoC). This direct comparison, utilizing a common hardware platform, provided a standardized metric for evaluating the SDHC’s performance gains. By testing read and write throughputs under identical conditions, researchers were able to isolate the SDHC’s contributions to data transfer speed, demonstrating its potential to significantly outperform traditional serial communication methods in embedded systems. The benchmarking process served not only to quantify performance improvements but also to highlight the SDHC’s efficiency in resource utilization when contrasted with SPI and I2C implementations.

Performance profiling of the CVA6 core during SDHC operation revealed the significant impact of the Fence instruction – a mechanism ensuring memory operation completion before subsequent instructions execute. Analysis demonstrated that while crucial for data integrity, the Fence instruction introduced latency, becoming a key bottleneck in overall throughput. This pinpointed specific code segments where instruction reordering or alternative synchronization techniques could potentially mitigate this overhead. Further optimization efforts are therefore focused on strategically minimizing Fence instruction usage without compromising data consistency, promising enhanced performance in memory-intensive applications and contributing to a more efficient open-source embedded system architecture.

Performance evaluations reveal the newly developed Serial Digital Host Controller (SDHC) substantially surpasses the capabilities of Serial Peripheral Interface (SPI) communication, demonstrating a remarkable up to 24.9x improvement in read throughput and an 11.3x increase in write throughput. These gains aren’t merely theoretical; they translate directly into faster data access and processing within embedded systems. Such a substantial performance boost unlocks possibilities for more complex and data-intensive applications on resource-constrained devices, enabling everything from enhanced multimedia capabilities to more sophisticated sensor data logging and analysis. The SDHC’s demonstrated efficiency establishes it as a compelling alternative for developers seeking to maximize performance and responsiveness in their embedded designs.

Beyond substantial gains in read and write throughput, the newly developed Serial Digital Host Controller (SDHC) demonstrates a remarkable efficiency in resource utilization. Benchmarking reveals that this controller requires only 24.2 thousand gate equivalents (kGE), representing a 3.6x reduction in area compared to a functionally equivalent Serial Peripheral Interface (SPI) peripheral which demands 86 kGE. This minimized footprint extends to the system’s boot Read-Only Memory (ROM), where the SDHC’s contribution is reduced from 8 kGE to 4.2 kGE. Such significant decreases in both hardware area and boot ROM requirements allow for the creation of more compact, power-efficient, and cost-effective embedded systems, opening possibilities for deployment in resource-constrained environments and devices.

The development of this optimized storage controller represents a significant advancement for the open-source embedded systems landscape. By delivering substantial gains in both performance and resource efficiency – achieving up to 24.9x faster read throughput while drastically reducing hardware footprint – the controller unlocks new possibilities for complex applications on constrained devices. This isn’t merely an incremental improvement; the reduced gate equivalent (GE) count and lessened boot ROM requirements allow for the integration of more sophisticated features and functionalities into open-source projects. Consequently, developers gain access to a storage solution that empowers them to build more capable, energy-efficient, and ultimately, more innovative embedded systems, fostering a more robust and accessible ecosystem for hardware development and experimentation.

The presented work embodies a principle of reduction. Optimizing the SD host controller for the Cheshire RISC-V SoC necessitates a ruthless paring away of unnecessary complexity. Performance gains, achieved through efficient cache management and minimized area usage, aren’t born of accretion, but subtraction. As G.H. Hardy observed, “The essence of mathematics lies in its simplicity.” This aligns directly with the core idea of the implementation – to deliver persistent storage access that is not merely functional, but elegantly streamlined. Clarity is the minimum viable kindness, and this design reflects that-a focused solution, stripped of extraneous elements.

Further Refinements

The pursuit of efficient persistent storage inevitably reveals the limitations of abstraction. This work demonstrates a pragmatic optimization of the SDHC for RISC-V, achieving gains through focused implementation. Yet, the underlying tension remains: the SD card interface, designed for removable media, imposes constraints on the tightly coupled storage expected within a System-on-Chip. Future efforts would benefit not from further layers of caching or complexity, but from a rigorous examination of alternative interfaces, or even entirely novel storage paradigms better suited to the SoC’s inherent architecture.

The open-source nature of this implementation offers a distinct advantage. However, true progress demands not merely accessible designs, but minimal designs. The tendency to accumulate features, even those offering marginal benefit, must be resisted. The next iteration should prioritize a ruthless pruning of unnecessary components, seeking a core controller stripped to its essential functions – a testament to the power of subtraction.

Ultimately, the value lies not in the speed of data transfer, but in the reduction of cognitive load. A simpler controller is easier to verify, easier to maintain, and, paradoxically, easier to improve. The goal is not to build a perfect SDHC, but to build one so transparent, so fundamentally clear, that its limitations become self-evident, and its potential for adaptation, limitless.

Original article: https://arxiv.org/pdf/2603.11849.pdf

Contact the author: https://www.linkedin.com/in/avetisyan/

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2026-03-15 17:50